• Anouncements
• Grades
• Administrative Information
• Lectures
• Homeworks
• In Class Quizes
• Lab Assignments
• Additional Study Notes
• Miscellaneous
• Other References
• Special Topics in CPE: Verilog HDL Modeling and Synthesis
  Informational Resources on the Internet

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Announcements

• ALL ENCE 3830/4500 Students PLEASE be advised that it is YOUR responsibility to initially obtain and frequently monitor the Tentative Course Schedule...
• ALL ENCE 3830/4500 Students PLEASE be advised that Homework #6 has been assigned and is due on Mon. 5/8/00 at the beginning of class!!!
• ALL ENCE 3830/4500 Students PLEASE be advised that Wed. 2/16/00 we will have the 1st quiz (please see the Reading and Homework list Columns in the Tentative Course Schedule for more details).
• ALL ENCE 3830/4500 Students PLEASE be advised that Lab #1 has been assigned and is due on Wed. 2/16/00 at the beginning of class
• ALL ENCE 3830/4500 Students PLEASE be advised that the ENCE 3830/4500 class meeting is as follows:
• Class meeting time: MW 7:15 - 8:45pm
• Class meeting location: Knudson Hall(CMK), Rm. 309
• Office hours: T 6:30pm-8:30pm Knudson Hall(CMK), Rm. 307
  or by appointment scheduled by phone
  or by appointment scheduled by email to meet in the course chat room
• ALL ENCE 3830/4500 Students PLEASE remember to get a copy of the following course related documents from the web:
• ENCE 3830/4500: Special Topics in CPE: Verilog HDL Modeling and Synthesis Course Overview
• ENCE 3830/4500: Special Topics in CPE: Verilog HDL Modeling and Synthesis Syllabus
• ENCE 3830/4500: Special Topics in CPE: Verilog HDL Modeling and Synthesis (Tentative) Schedule
• ALL ENCE 3830/4500 Students PLEASE remember to perform the following course preparation tasks:
• Send email to me so that I can establish a class mailing list
• ENGR 3320: Spring Quarter Final Project Presentation Scheduling





Mon. 5/22/00
5:00pm	Julie Reed	6:00pm	Michael O'Relley
5:10pm	Faisal Khan	6:10pm	Available
5:20pm	Constanza Carrillo	6:20pm	Available
5:30pm	Chris Cranfield	6:30pm	Available
5:40pm	Yohannes Iyassu	6:40pm	Available
5:50pm	Turk Nejress	6:50pm	Available

ALL ENCE 3830/4500 Students PLEASE make sure that your Verilog HDL labs/programming assignments conform to the programming style guide line found on this web page!!

ENCE 3830/4500: Grades

• ALL ENCE 3830/4500 Students, Grades will be available from this web page!!

Administrative Information

• Administrative Info (contact info, books, grading policy, etc)
• Course Syllabus (topics covered, etc)
• Scheduled Course Readings, and Homeworks
• Course Mailing List (ence3830@cs.du.edu)
• Current Grades

Lectures

First 5 weeks

Second 5 weeks

Week 1: Lecture #1: (Wed.. 3/22/00) VHDL / Verilog Week 2: Lecture #2: (Mon. 3/27/00) VHDL / Verilog Lecture #3: (Wed. 3/29/00) VHDL / Verilog Week 3: Lecture #4: (Mon. 4/3/00) VHDL / Verilog Lecture #5: (Mon. 4/5/00) VHDL / Verilog Week 4: Lecture #6: (Mon. 4/10/00) VHDL / Verilog Lecture #7: (Wed. 4/11/00) VHDL / Verilog Week 5: Lecture #8: (Mon. 4/17/00) VHDL / Verilog Lecture #9: (Wed. 4/19/00) VHDL / Verilog

Week 6: Lecture #10: (Mon. 4/24/00) VHDL / Verilog Midterm Exam: (Wed. 4/26/00) Week 7: Lecture #11: (Mon. 5/1/00) VHDL / Verilog Lecture #12: (Wed. 5/3/00) VHDL / Verilog Week 8: Lecture #13: (Mon. 5/8/00) VHDL / Verilog Lecture #14: (Wed. 5/10/00) VHDL / Verilog Week 9: Lecture #15: (Mon. 5/15/00) VHDL / Verilog Lecture #16: (Wed. 5/17/00) VHDL / Verilog Week 10: Lecture #17: (Mon. 5/22/00) VHDL / Verilog Lecture #18: (Wed. 5/24/00) VHDL / Verilog

Homeworks

First 5 weeks	Second 5 weeks
Homework #1 / Solution --> Homework #2 / Solution Homework #3 / Solution Homework #4 / Solution	Homework #5 / Solution Homework #6 / Solution Homework #7 / Solution Homework #8 / Solution

In Class Quizes

First 5 weeks	Second 5 weeks
Quiz #1 / Solution Quiz #2 / Solution Quiz #3 / Solution Quiz #4 / Solution	Quiz #5 / Solution Quiz #6 / Solution Quiz #7 / Solution Quiz #8 / Solution

Lab Assignments

• Lab Assignment Style Guidelines

First 5 weeks	Second 5 weeks
Lab Assignment #1 Lab Assignment #2 Lab Assignment #3	Lab Assignment #4 Lab Assignment #5 Lab Assignment #6

Final Project Presentation and Report Information

Below is the list of Final Project document templates that specifiy the minimum mandatory sections and/or slides to have for you Final Project Architecture Report and Presentation. Please note, that these specifications contained in the templates below are minimum and I expect that all of your projects will contain more detail described in subsections and/or appendices.

• Final Project Report Template
• Final Project Presentation Template

Additional Study Notes

• An Introduction to the Concepts of Timing and Delays in Verilog
• An Online Verilog Manual
• A Hardware Designer's Guide to Verilog

Miscellaneous

• Verilog FAQ
• Alternative Verilog FAQ

Other References

• Text Book: HDL Chip Design -- Douglas J. Smith -- First Edition (Doone Publications)
• Text Book: A Verilog HDL Primer -- J. Bhasker -- First Edition (Doone Publications)

Special Topics in CPE: Verilog HDL Modeling and Synthesis
Informational Resources on the Internet

• Cadence home page
  
• Simucad home page
  
• Synopsys home page
  
• Xilinx home page
  
• Open Verilog International(OVI) home page
  
• International HDL Conference home page
  
• Verilog.net free tools home page
  

 

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This page is maintained by Christopher A. Gantz (cgantz@.du.edu).